The disclosed subject matter relates generally to computers, and, more particularly, to the use of staggered read operations for multiple-operand instructions.
Typical x86 instructions require only two operands. Therefore, conventional register file hardware includes two read ports to support reading two source operands per instruction scheduled. Recent Intel AVX ISA extensions contain instructions that require a third source operand. For example, blend instructions (VBLEND*) and fused-multiply-add instructions (VFMADD*, VFMSUB*, VFNMADD*, VFNSUB*) are three operand instructions.
Adding a third dedicated read port to the register file hardware to support a three operand instruction increases the time delay of the register file read and also significantly increases the power consumption and area required by the register file. The register file read-delay, area, and power consumption are parameters typically directly linked to performance, because these parameters influence the maximum number of rename registers that can be supported.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.